1. Field of the Invention
The present invention relates to a receiver of a direct conversion structure. More particularly, the present invention relates to an image rejection apparatus capable of rejecting an image signal interfering with an original signal using a sign-sign Least Mean Square (LMS) algorithm having an adaptive step size in the case in which there is a mismatch between In-phase (I)/Quadrature (Q) signal paths in a quadrature receiver of a direct conversion structure.
2. Description of the Related Art
In a receiver of a direct conversion structure, Radio Frequency (RF) signals are down-converted into Intermediate Frequency (IF) signals using complex I/Q mixers not having an image filtering function. During such a down-conversion process, image signals are generated in signal bands because of I/Q path gain and phase errors.
An image rejection apparatus also called a Hartley architecture, which is one of conventional techniques for rejecting image signals in the signal bands, is described below with reference to FIG. 1.
FIG. 1 is a configuration diagram of the conventional image rejection apparatus having a Hartley architecture.
As shown in FIG. 1, the image rejection apparatus of a Hartley architecture includes two frequency converters 10 and 12, two low-pass filters 14 and 16, a phase shifter 18, and an adder 20.
Input radio signals RF in are down-converted into intermediate frequency signals through the two frequency converters 10 and 12. Here, the signals inputted to the frequency converters 10 and 12 are down-converted by a signal (sin ωLOt) of a sine waveform and a signal (cos ωLOt) of a cosine waveform, respectively. Accordingly, the phase difference of the signal between two paths is 90° so that the signal is divided into I and Q components.
The signals down-converted by the frequency converters 10 and 12 pass through the respective low-pass filters 14 and 16 so that high frequency components are rejected from the signals. Consequently, only intermediate frequency signals and image signals are left.
Next, the phase of the signal only in one of the two paths is shifted by 90° through the phase shifter 18. The resulting signal is added to the signal in the other of the two paths through the adder 20. Consequently, an intermediate frequency signal IF out from which the image signals have been rejected is outputted through the adder 20.
The above-described image rejection apparatus of a Hartley architecture is problematic in that image signals are not fully rejected if gain error or phase error occurs between the two paths due to variation in the process or a change in the channel because it includes analog circuits.
FIG. 2 is a configuration diagram of a conventional image rejection apparatus including digital circuits.
As shown in FIG. 2, the conventional image rejection apparatus consisting of digital circuits includes an image rejecter 30 and an error detector 40.
The image rejecter 30 includes four multipliers 31, 32, 33, and 34 and two adders 35 and 36. The image rejecter 30 is configured to receive I′/Q′ signals (i.e., real signals of ideal I/Q signals, generated due to the occurrence of gain error or phase error because of variation in the process or a change in the channel), to restore the received I′/Q′ signals to the ideal I/Q signals using the four multipliers 31, 32, 33, and 34 and the two adders 35 and 36, and then to output I″/Q″ signals from which image signals have been rejected. In FIG. 2, α denotes the gain error, and θ denotes the phase error.
The image rejecter 30 requires accurate gain error and accurate phase error for the image rejection function. To accurately estimate the gain error and the phase error, the error detector 40 is used.
The error detector 40 receives the I″/Q″ signals outputted from the image rejecter 30, detects gain error and phase error in the received I″/Q″ signals, and feeds back the detected gain error and the detected phase error to the image rejecter 30.
To this end, the error detector 40 includes two comparators 41 and 42, two XNOR gates 43 and 44, two 20-bit up/down counters 45 and 46, and two 9-bit up/down counters 47 and 48.
The error detector 40 including the above elements finds (I″)2−(Q″)2 from the received I″/Q″ signals, estimates the gain error by performing low-pass filtering processing for the (I″)2−(Q″)2, finds I″Q″, and estimates the phase error by performing low-pass filtering processing for the I″Q″.
In the error detector 40 shown in FIG. 2, the signs of (I″)2−(Q″)2 and I″Q″ are respectively found and used instead of (I″)2−(Q″)2 and I″Q″. The sign of (I″)2−(Q″)2 is found by performing a sign multiplication function (for example, an XNOR operation) for the sign of (I″+Q″) and the sign of (I″−Q″), and the sign of I″Q″ is found by performing a sign multiplication function (for example, an XNOR operation) for the sign of I″ and the sign of Q″. To this end, the error detector 40 includes the two comparators 41 and 42 and the two XNOR gates 43 and 44.
Further, each of the two 20-bit up/down counters 45 and 46 performs a low-pass filtering function. The two 9-bit up/down counters 47 and 48 store the estimated gain error and the estimated phase error and feed back values thereof to the image rejecter 30.
For detailed information pertinent to FIG. 2, reference can be made to “A Complex Image Rejection Circuit with Sign Detection Only” by Supisa and Bang-Sup Song (IEEE Journal of Solid-State Circuit, Vol. 41. No. 12, December 2006).
Referring to FIG. 2, the above-described image rejection apparatus is advantageous in that it has a simple construction because simple hardware is used to reject images on signals, but is problematic in that the adaptation time is long in order to obtain a high image rejection ratio because the size of a step must be small for accurate error estimation. Further, the image rejection apparatus of FIG. 2 is configured to accumulate errors at DC and is problematic in that, if signals or offset exists at DC, the image rejection ratio is lowered because error cannot be accurately estimated.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.